1. Field of the Invention
The present invention relates to a thin film magnetic memory device, and more particularly, to a thin film magnetic memory device including a memory cell having a magnetic tunnel junction (MTJ).
2. Description of the Background Art
Recently, an MRAM (Magnetic Random Access Memory) device has attracted attention as a new-generation non-volatile memory device. The MRAM device is a non-volatile memory device storing data in a non-volatile manner with a plurality of thin film magnetic elements formed on a semiconductor integrated circuit, and allowing random access to each thin film magnetic element.
Particularly, it has been disclosed that a performance of the MRAM device is remarkably enhanced by employing a thin film magnetic element using the magnetic tunnel junction as a memory cell in recent days.
FIG. 8 is a schematic diagram showing a configuration of the memory cell having the magnetic tunnel junction (hereinafter, simply referred to as an “MTJ memory cell”).
Referring to FIG. 8, the MTJ memory cell includes a tunneling magneto-resistance element TMR having an electric resistance variable in accordance with a data level of magnetically written storage data, and an access transistor ATR. Access transistor ATR is connected in series to tunneling magneto-resistance element TMR between a bit line BL and a source voltage line SL. Typically, a field-effect transistor formed on a semiconductor substrate is employed as access transistor ATR.
Provided for the MTJ memory cell are bit line BL and a digit line DL for feeding a data write current in a different direction respectively in data write, a read word line RWL for instructing data read, and source voltage line SL for pulling down tunneling magneto-resistance element TMR to ground voltage GND in data read. In data read, in response to turn-on of access transistor ATR, tunneling magneto-resistance element TMR is electrically coupled between source voltage line SL and bit line BL.
FIG. 9 is a conceptual view illustrating a data write operation into the MTJ memory cell.
Referring to FIG. 9, the tunneling magneto-resistance element TMR includes a ferromagnetic material layer FL having a constant, fixed magnetic direction (hereinafter, simply referred to as a “fixed magnetic layer”), and a ferromagnetic material layer VL magnetized in a direction in accordance with an externally applied magnetic field (hereinafter, simply referred to as a “free magnetic layer”). A tunneling barrier (a tunneling film) TB formed with an insulating film is provided between fixed magnetic layer FL and free magnetic layer VL. Free magnetic layer VL is magnetized in a direction identical or opposite to fixed magnetic layer FL, in accordance with a level of the written storage data. These fixed magnetic layer FL, tunneling barrier TB, and free magnetic layer VL form the magnetic tunnel junction.
The electric resistance of tunneling magneto-resistance element TMR varies in accordance with a relative relation in respective magnetic directions of fixed magnetic layer FL and free magnetic layer VL. Specifically, the electric resistance of tunneling magneto-resistance element TMR is set to a minimum value Rmin when the fixed magnetic layer FL is magnetized in a direction identical to (in parallel with) that of free magnetic layer VL, while it is set to a maximum value Rmax when one of the above layers is magnetized in a direction opposite (antiparallel) to the other.
In data write, read word line RWL is inactivated, and access transistor ATR is turned off. In such a state, the data write current for magnetizing free magnetic layer VL flows in a direction in accordance with the level of the write data, respectively through bit line BL and digit line DL.
FIG. 10 is a conceptual view showing a relation of the data write current with the magnetic direction of the tunneling magneto-resistance element in data write.
Referring to FIG. 10, the abscissa H (EA) represents a magnetic field applied in a direction of an easy axis (EA) in free magnetic layer VL within tunneling magneto-resistance element TMR. On the other hand, the ordinate H (HA) represents a magnetic field acting in a direction of a hard axis (HA) in free magnetic layer VL. Magnetic fields H (EA) and H (HA) correspond to respective one of two magnetic fields produced by the current flowing in bit line BL and digit line DL respectively.
In the MTJ memory cell, the fixed magnetic direction of fixed magnetic layer FL extends along the easy axis of free magnetic layer VL, while free magnetic layer VL is magnetized along the easy axis in a direction parallel or antiparallel (opposite) to fixed magnetic layer FL, in accordance with the level of the storage data (“1” and “0”). The MTJ memory cell can store 1-bit data (“1” and “0”), corresponding to two magnetic directions of free magnetic layer VL.
The magnetic direction of free magnetic layer VL can be rewritten only when the sum of the applied magnetic fields H (EA) and H (HA) reaches a region outside an asteroid characteristic line shown in FIG. 10. In other words, if the applied data write magnetic field has intensity within a region inside the asteroid property line, the magnetic direction of free magnetic layer VL does not vary.
As shown with the asteroid characteristic line, a magnetization threshold value necessary for varying the magnetic direction along the easy axis can be lowered by applying a magnetic field in the direction of hard axis to free magnetic layer VL. When an operation point in data write is designed as in an example shown in FIG. 10, in the MTJ memory cell to which data is written, the data write magnetic field in the direction of the easy axis is designed to have an intensity HWR. In other words, a value of the data write current fed through bit line BL or digit line DL is designed so as to obtain data write magnetic field HWR. Generally, data write magnetic field HWR is shown with the sum of switching magnetic field HSW necessary for switching the magnetic direction and a margin ΔH. That is, it is shown with HWR=HSW+ΔH.
In order to rewrite the storage data in the MTJ memory cell, that is, the magnetic direction of tunneling magneto-resistance element TMR, the data write current at a prescribed level or higher should be fed through both digit line DL and bit line BL. Thus, free magnetic layer VL in tunneling magneto-resistance element TMR is magnetized in a direction parallel or opposite (antiparallel) to fixed magnetic layer FL in accordance with an orientation of the data write magnetic field along the easy axis (EA). The magnetic direction once written in tunneling magneto-resistance element TMR, that is, the storage data in the MTJ memory cell, is held in a non-volatile manner until new data write is carried out.
FIG. 11 is a conceptual view illustrating a data read operation from the MTJ memory cell.
Referring to FIG. 11, in the data read operation, access transistor ATR turns on in response to activation of read word line RWL. Thus, tunneling magneto-resistance element TMR is electrically coupled to bit line BL, while it is pulled down to ground voltage GND.
In such a state, when bit line BL is pulled up to a prescribed voltage, a memory cell current Icell in accordance with the electric resistance of tunneling magneto-resistance element TMR, that is, in accordance with the level of the storage data in the MTJ memory cell, passes through a current path including bit line BL and tunneling magneto-resistance element TMR. For example, by comparing memory cell current Icell with a prescribed reference current, the storage data can be read from the MTJ memory cell.
Here, generally, memory cell current Icell is designed to be lower by 1 to 2 digits than the above-described data write current. Therefore, it is unlikely that the storage data in the MTJ memory cell is inadvertently rewritten due to an effect of memory cell current Icell. In other words, non-destructive data read is possible.
FIG. 12 shows a first configuration example of the MTJ memory cell connected on the semiconductor substrate.
Referring to FIG. 12, access transistor ATR formed on a semiconductor substrate SUB includes impurity regions 110 and 120 which are of n-type, and a gate region 130. Impurity region 110 is electrically coupled to source voltage line SL via a metal film formed in a contact hole 131.
Digit line DL is formed in a metal interconnection layer provided above source voltage line SL. Tunneling magneto-resistance element TMR is disposed on the upper side of digit line DL. Tunneling magneto-resistance element TMR is electrically coupled to impurity region 120 in access transistor ATR via a strap 150 and a metal film formed in a contact hole 140. Strap 150 is provided so as to electrically couple tunneling magneto-resistance element TMR to access transistor ATR, and formed with a conductive material. Bit line BL is electrically coupled to tunneling magneto-resistance element TMR, and provided on the upper side of tunneling magneto-resistance element TMR.
Bit line BL through which the data write current and a read current is fed, and digit line DL through which the data write current is fed are formed with the metal interconnection layer. Meanwhile, since read word line RWL is provided so as to control a gate voltage of access transistor ATR, it is not necessary to actively feed the current. Therefore, in the viewpoint of higher integration, read word line RWL is generally formed in the same interconnection layer as gate region 130, using a polysilicon layer, a polycide layer or the like, without newly providing an independent metal interconnection layer.
FIG. 13 shows a second configuration example of the MTJ memory cell fabricated on the semiconductor substrate.
Referring to FIG. 13, the second configuration example is different in that source voltage line SL is not formed with the metal interconnection layer in order to reduce the number of the metal interconnection layers necessary in the structure of the MTJ memory cell. Impurity regions 110 corresponding to source side are electrically coupled to each other between access transistors ATR adjacent in a direction of row or column, and coupled to ground voltage GND, thereby acting as a source voltage line.
Accordingly, digit line DL and bit line BL formed in metal interconnection layers M2 and M3 respectively in the first configuration example shown in FIG. 12 are formed in metal interconnection layers M1 and M2 respectively. Thus, in the second configuration example, the number of metal interconnection layers necessary for forming these signal lines is reduced by one, compared to the first configuration example. Therefore, higher integration of the MTJ memory cell can be implemented.
FIG. 14 shows a third configuration example of the MTJ memory cell fabricated on the semiconductor substrate.
Referring to FIG. 14, the third configuration example is different in that digit line DL is disposed above the metal interconnection layer for bit line BL.
Accordingly, digit line DL and bit line BL formed in metal interconnection layers M1 and M2 respectively in the second configuration example shown in FIG. 13 are formed in metal interconnection layers M2 and M1 respectively. In other words, digit line DL is formed in the metal interconnection layer above the metal interconnection layer constituting bit line BL. Thus, as shown in FIG. 14, digit line DL can be formed above impurity region 120, not above gate region 130. Accordingly, a region for strap 150 can be made smaller, and the size of the transistor can further be reduced. Higher integration of the MTJ memory cell can further be improved.
As described above, the MRAM device can realize non-volatile data storage with the MTJ memory cell integrated and disposed on the semiconductor substrate. In each MTJ memory cell, tunneling magneto-resistance element TMR has an electric resistance variable in accordance with the magnetic direction rewritable by the applied data write magnetic field. Therefore, by associating electric resistance Rmax and Rmin of tunneling magneto-resistance element TMR with the level of the storage data (“1” and “0”) respectively, non-volatile data storage can be realized.
As described with reference to FIG. 11, data read in the MRAM device is carried out by detecting as a read current, memory cell current Icell reflecting the electric resistance of a selected memory cell, or another current in accordance with the memory cell current, for example, by a sense amplifier.
A number of transistors that are turned on in data read, however, are connected to such a path for the read current (hereinafter, referred to as a “read current path”). For example, in a configuration in which a word line is disposed corresponding to a memory cell row, while a bit line is disposed corresponding to a memory cell column, access transistor ATR in the selected memory cell is connected to a select bit line contained in the read current path. In addition, a column select gate provided corresponding to each bit line and selecting a corresponding bit line also turns on, and electrically connects the select bit line to the sense amplifier and the like.
Since the read current passes through the transistors that have turned on in the sense amplifier, the read current in accordance with the sum of the resistance of the transistors and the electric resistance of the selected memory cell is detected. Therefore, as the resistance of the transistors increases, the read current does not necessarily reflect the electric resistance of the selected memory cell, which may lead to misread. In addition, due to the effect of the resistance of the transistors, sensing operation may consume time, and high-speed data read may adversely be affected.
Particularly, in the general MTJ memory cell, a value for the electric resistance is of the order of several tens of KΩ, and the voltage applied to the MTJ memory cell in data read is suppressed approximately to 0.5V, considering reliability and the like of the tunneling film (insulating film). Therefore, the above read current remains at the order of micro ampere (μA: 10−6A). Accordingly, in order to carry out high-speed data read, an effect of the resistance of those transistors should be suppressed so as to sufficiently secure the read current difference.